
Our Team
Executive board
-
Dr. Richard Izak
Founder & Technical Lead
Since his electrical engineering studies over 30 years ago, fascinated by ADC/DAC circuits, Richard pursued the goal of innovate semiconductor data converters. From academics, through 12 years of design consulting to founding Continium, he attracted most experienced semiconductor veterans in our team to innovate the data converter market by strengthening ASIC product made in Europe.
-
Gerhard Mittereger
CTO
Gerhard is a world-leading authority in chip design, holding the global Figure of Merit record for ADCs from 2006 to 2014. As CTO, he draws on extensive experience at Xignal, National Semiconductor, Intel, and MediaTek. A frequent IEEE ISSCC committee member with over 700 citations, he also co-developed the first commercially successful CTSD ADC chip.
-
Jozef Bujnovsky
CEO & COO
As CEO and COO of Continium, Jozef combines deep entrepreneurial experience with a strong track record in international business growth. He co-founded INOVATO, a technological business cluster fostering innovation across industries, and co-created HDTS, a world-leading ice hockey testing system now active in over 18 countries. Beyond Europe, he has driven market entry and business development projects across Asia and the Americas, overseeing partnerships and scaling strategies that brought advanced technological solutions to new markets.
-
Peter Hospodar
CFO & Business Development
Peter brings extensive experience in financial and management accounting, honed through consulting roles at Big 4 firms across the DACH region. As co-founder of a Slovak technology incubator, he developed and executed financing and commercialization strategies for startups, bridging innovative ideas with market realities. His strong track record in performance improvement and venture development underscores his ability to drive growth, deliver impactful business transformations, and mentor emerging entrepreneurial teams navigating complex market challenges.
-
Gabriel Pozsonyi
Commercial Officer
Gabriel offers over 20 years of leadership across the semiconductor supply chain, coupled with deep expertise in corporate management and strategic partnerships. At Intel Capital, he analyzed emerging business models and technologies, informing pivotal investment moves that shaped industry direction. He also led the commercial scale-up of a pharma startup and negotiated complex contracts with front-end, back-end, and EDA suppliers, securing essential collaborations and steering businesses through critical growth stages with long-term operational resilience.
Team of specialists
-
Richard
Founder & Technical Lead
Richard studied electrical engineering at TU Ilmenau. Already during his diploma thesis in 1995, he designed his first ADC for a UV sensor dosimeter. In 1996, upon his Dipl.-Ing./MSc graduation, Richard started his post-graduate research in the field of analog neuromorphic auditory VLSI systems and implemented a different CMOS version of spiking neurons. In 1999, he joined the semi-industrial research institute IMMS Erfurt as ADC group leader and analog designer. During his five years of leadership, he established the ADC group from the ground up into a skilled design team that successfully completed industrial contracts (Siemens, GEMAC/AMAC) and research projects with first-time-right silicon ADCs. After defending his PhD thesis externally in 2004, he joined Heidenhain Motion Control as an analog IC designer for rotary encoders. In 2009, he returned to the data converter IC industry by joining the National Semiconductor design center for CTSD (continuous-time Sigma Delta) ADCs for wireless base stations. Since 2011, he has been an entrepreneur, successfully working as an analog and mixed-signal ASIC design consultant in Munich. He built a skilled ASIC design team from scratch and eventually founded Continium Technologies.
-
Gerhard
CTO
Gerhard holds an MSc degree in electrical engineering and is one of the worldwide leading analog and system-level designers, researchers, and innovators in chip design (ADC/DAC design), with over 27 years of experience. He began his career with the Infineon analog group. His expertise is evidenced by several publications and his selection to the IEEE ISSCC program committee for data converters (2011–2017), a group of peer experts that selects the top papers for presentation at the annual International Solid-State Circuits Conference in San Francisco.Gerhard has an excellent reputation in both the data converter chip industry and academic research. His wireless ADC products and research outcomes remain best-in-class. He was the project and design manager for the world’s first Bandpass Sigma Delta ADC developed for BTS wireless receivers at National Semiconductor. Since 2010, he has served as the technical lead in the research and development department for receiver ADCs for smartphones at Intel Mobile Communications. Since 2015, he has also been consulting for wireless companies in Europe and the USA, alongside his role as a technical leader in Continium’s design team.
-
Reinhard
ADC/DAC System Architect and Mixed-Signal Designer
Reinhard studied Electrical Engineering at TU Chemnitz and started 1974 working at Funkwerk Erfurt as system engineer for process control in the VLSI foundry. Since 1977 he changed to CAD design group working on in-house system level and logic simulators for CPU-clones of U880, i286 and Micro-VAX. In 1999 he joined the Institute IMMS and Richard’s ADC group where he was responsible for system level design of switched-capacitor (SC) ADC and their behavioral simulation using SpectreHDL / VerilogA beside of his everyday digital HDL design. During his 14 years at IMMS he developed different 12-15b cyclic and pipeline ADCs in different technologies (CMOS and SOI) for industrial customers as well as research projects. Since 2013 he started his design consulting business and joined Continium Technologies as initial member of the design team. In Continium’s team Reinhard is leading scripting programmer (data base conversion, netlist post-processing, ADC’s spectral FFT analysis, parasitic extraction data optimization, CAD-add-ons) as well as technical lead digital designer (IIR & FIR filter; DWA/DEM mismatch shaper for DACs). Reinhard has broad experience with hardware description languages (Verilog / VHDL), analog behavioral modeling (VerilogA/VHDL-AMS), MATLAB system level design, fundamental digital and analog CAD design flow of Cadence, Mentor/Tanner, Synopsys.
-
Norbert
Physical Mask Designer (Layout lead)
Norbert holds degree in electrical engineering (TU Munich) and has about 35 years of international, hands-on experience in the Semiconductor industry and possess expert knowledge of physical design for analog/mixed signal ICs. He is a self starter, budget and resource conscious, self motivating, used to working independently and to deadlines with minimum of supervision but maximum of customer liaison. He has in-depth understanding of backend EDA tool flow (Cadence Virtuoso XL, QRC, Mentor Graphics Calibre/Dracula, Tanner L-edit basics, some Synopsys tools) and design methodologies covering technology portfolio of low-voltage CMOS (down to 20nm) as well as high voltage bipolar, 60V HV-CMOS, 120V BCD, 200V SOI and up to several hundred Volts in single power transistor technologies. In his design consulting career he worked as layout team lead (managing up to 20 men) with several leading edge companies like ST-Micro, Siemens/Infineon, Texas Instruments, Intel, Bosch/Sensortec, Dialog, Rohde&Schwarz and supported several product families of hearing aids and audio processors over a whole decade. His design experience covers automotive applications (full custom layout circuits like LDO, Boost Converter, airbag controlling applications, LIN, CAN, door module power, Hall sensor, LOW/HIGH-side switches, HALF-/FULL bridge systems, Coreless Transformer applications), microcontroller and processors, hearing aids, full custom layout of EEPROM periphery as well as technology transfers. He worked together with Continium team members on several project as physical mask design lead, especially the 20b current-steering DAC.
-
Ramesh
Layout Engineer
Ramesh holds an MSc from Manchester University and began his career in the UK with GEC Hirst before moving to Eurosil and LSI Logic in Germany. With over 30 years in semiconductor design and 25 years as a freelance physical designer, he has consulted for top European clients including Texas Instruments, STMicroelectronics, Infineon, Intel, and Bosch. Experienced in Bipolar, BCD, and CMOS down to 3nm finfet, he is proficient in Cadence, Mentor, and Tanner tools, with design expertise spanning high-voltage, low-power, and RF circuits. Based in Germany, Ramesh brings deep insight into advanced IC design.
-
Danijel
Analog Design Engineer
Danijel holds an MSc in Microelectronics from STU Bratislava, specializing in IC design. He began his career at ON Semiconductor, where he worked for over 20 years on chip development for automotive and multimarket applications such as LDOs, DC-DCs, and PMICs. He has hands-on experience with bipolar, BiCMOS, and CMOS technologies down to the 65nm node, and is proficient in EDA and simulation tools like Cadence Virtuoso, Calibre, and Spectre. Danijel also led small development teams and mentored junior engineers. He joined Continium Technologies in 2024 to support analog IC development.
-
Stefan
Analog Design Engineer
Stefan graduated at STU Bratislava in 2003 (MSc in radioelectronics). He has been working for more than 17 years in the semiconductor industry joining STMicroelectronics and ON Semiconductor in the past. His design expertise relates to power management circuitry in BiCMOS, CMOS and BCD technologies for consumer and automotive market. He has an in-depth understanding of the IC design flow, from schematic capture including behavioral VerilogA modeling, through simulation/verification and layout/post layout verification to validation. Stefan joined Continium team in early 2024.
-
Juraj
Digital Design Engineer
Juraj holds a Master's degree in Electrical Engineering, specializing in Electronics and Photonics, from the Slovak University of Technology in Bratislava (STU), earned in 2024. During his graduate studies, he gained two years of industry experience at the onsemi Development Center in Bratislava, where he interned in digital design and verification. At Continium Technologies, Juraj embraced a new challenge by expanding his expertise into the realm of physical design.
-
Lubos
Layout Engineer
Lubos graduated from the Slovak University of Technology, Faculty of Electrical Engineering and Information Technology, in 2018. He began his career as a Junior Embedded Programmer before advancing to a Senior STM32 Programmer and PCB Designer at Sigrow BV, where he focused on low-power IoT and LoRa-based wireless sensor systems. With deep expertise in embedded hardware and firmware integration, Lubos brings precision and innovation to every layout design.
-
Juraj
Analog ASIC Design Engineer
Juraj earned his degree in microelectronics from STU Bratislava in 1991 after preparing his thesis at TU Ilmenau in Germany. He began his career as a hardware and automation engineer before joining IMMS Erfurt in 2001, leading optoelectronic IC projects for DVD/BluRay in cooperation with Melexis and Toshiba. Skilled in Cadence design flows and analog circuits, he later worked in PLC programming and automation for major automotive clients. Juraj joined Continium’s design team in 2020, bringing versatile expertise in IC and industrial systems.
-
Tomas
Digital Design Engineer
Tomas has contributed to several projects involving RTL design and verification, demonstrating strong skills in Verilog and SystemVerilog. He is comfortable working across the hardware-software boundary, often integrating low-level firmware with simulation and test environments. His background in machine learning and modeling allows him to approach hardware challenges with a data-driven mindset. He is also experienced in developing custom tools and automation scripts in Python and Bash to streamline development workflows on Linux platforms. With a solid foundation in computer architecture and system-level design, Tomas consistently delivers robust and efficient solutions in both hardware and software domains.
-
Andy
RF Design Expert
Andy earned his MSc in electrical engineering from STU Bratislava in 1996 and spent six years on postgraduate research at TU Ilmenau, specializing in RF and EMC design of microcontroller applications and ceramic multi-chip modules. His work included advanced RF characterization up to 18 GHz and simulation of power/ground structures. Andy later worked in Bratislava on EMC certification, voltage regulator testing, and 4kV power supplies for demanding industrial applications. He joined Continium’s design team in 2023, contributing strong analytical and design expertise.
-
Daniel
FPGA Application and Digital Design Engineer
Daniel holds an MSc in microelectronics from STU Bratislava and completed postgraduate research at the University of Bournemouth on neural networks in ASICs and FPGAs. With 25 years of experience in FPGA, CPLD, and microprocessor-based systems, he began his career at Celoxica Ltd. UK, later leading its hardware group. Today he consults for IoT companies in the UK and USA, specializing in embedded software, PCB design, and real-time systems across a wide range of platforms and industries.
-
Olaf
RF Application and Test Engineer
Olaf studied engineering at TU Chemnitz and Berlin and began his career at Siemens, developing RF systems for early GSM mobile phones. He later worked at CSEE Neuchatel as an RF test engineer and at Infineon (later Lantiq) in Munich on Verigy V93000 platforms and advanced wireline applications. Since 2014 he has consulted on RF, EMC, WLAN, DECT, and V93000 test boards. Olaf’s work at Continium uniquely combines RF application expertise with deep experience in ADC and DAC spectral testing and validation.
-
Rado
Layout expert
He holds MSc degree in electrical engineering from TU Kosice in 2004 and he is layout methodology and design expert with more than 16 years experience in high competitive companies (STmicro, ST-Ericsson, Huawei, Infineon and Dialog). He is leading physical designer of various products in wide range of technologies from 350nm down to 28nm CMOS, experienced in power management units as well as in finger touch screen controller and ADCs. Since 2017 he started his freelance design consultancy and joined Continium team in 2021.
-
Robert
Project Manager
Róbert earned his PhD in Public Policy from Comenius University in 2024, studying expert-politician dynamics during COVID-19. As Head of International Relations at the university’s Faculty of Social and Economic Sciences, he managed global partnerships and capacity-building projects. At Continium, Róbert oversees ongoing projects and prepares European grant proposals, applying strategic planning and project management skills to advance research and innovation initiatives.
-
Barbora
Project Manager
Barbora joined Continium from biotech startup MultiplexDX, where she led a project for Slovakia’s Ministry of Health during COVID-19. She excelled in project coordination, team management, and communications, also supporting sales, fundraising, and EU projects. Earlier, she helped organize one of the largest CEE startup competitions, securing Michael Siebel of Y Combinator. Barbora studied abroad in Barcelona and Turkey and interned in Brussels during Slovakia’s first EU Council Presidency.
-
+ many more
Become a part of this team.
◖ OUR competence
Innovative ADC/DAC Designs Across Leading Technology Nodes
Our team delivered world-class performance in analog and mixed-signal design, with a focus on high-speed, high-resolution data converter systems. Below is a glimpse into our expertise.
Examples of Our Designs
12-14 bit 20 MHz Lowpass CTSD ADC silicon products up to 8 channels
Smartphone Wi-Fi/Cellular Rx Baseband AFE with data converters and digital filters
20 bit 100 MS/s current steering Sigma-Delta DAC
16-bit cyclic ADC/DAC up to 1 MS/s Nyquist sampling rate
SAR & Pipeline high-speed data converters
10GB/s SERDES in CMOS process for SDH/SONET applications
GHz high-performance PLL synthesizer and divider with very low phase noise
Smartphone modem: 3rd Order CTSD ADC with integrated LNA & mixer
World’s first BTS Bandpass CTSD ADC digitizing the IF (130nm CMOS)

8 channel CTSD ADC product

20 bit l00MS/s current steering DAC on wafer
Technology Nodes
0.6µm
0.35µm
250nm
180nm
130nm
65nm
We started with chip design when the transistor was at 3µm and we have developed until now:
28nm
22nm
16nm
14nm
12nm
7nm
Foundries
TSMC
GloFo
X-FAB
Intel
Infineon
UMS
Materials