Digital HDL Circuit Designer
Location:
Košice and Bratislava/ Slovakia and Germany
Responsibilities:
Digital logic design and implementation of FIR/IIR/Wave-digital decimation filters or high-speed data interfaces (JESD204, SPI, PCI) and serializers based on existing specifications in nano-meter CMOS/FinFET technologies
HDL (Hardware description language: Verilog/VHDL) Synthesis for integrated circuits (IC) or design experience with FPGA digital programmable devices (Field programmable gate array: Xilinx, Altera)
Logic verification and logic simulation on the RTL level or on the transistor level
Static Timing Analysis (STA), Power estimation and optimization, circuit analysis & debugging
Test pattern generation experience using ATPG and logic simulation tools and support of test program development
Generation of library views and macro preparation (e.g. VHDL entity)
Low power and asynchronous digital design techniques
Behavioural modeling of mixed-signal blocks (Verilog-AMS, VHDL-AMS) providing an interface to analog design engineers
Signal processing in MATLAB: digital filter design, spectral analysis of digital filters
Guidance and supervision of the P&R layout mask process
Lab characterization and debugging of own digital modules
Qualifications (professionals or graduates):
University: Master’s or Ph.D. degree in Electrical Engineering or Communication Technologies
Good understanding of VLSI and/or ASIC methodology and HDL design flow
Main focus on digital design and digital filter design
Experience in CMOS/FinFET logic design on a cell level
Formal tools and Verification methods experience including modeling in C/C++, SystemC
CAD digital skills required (Cadence, Mentor Graphics, or Synopsys)
Unix/Linux and Perl/C++ skills required
Experience with internet-based home office work (TeamViewer or WebEx meetings)
Apply here:
Send us your CV to service@continiumtech.com
